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authors Jabri, Marwan A. and Skellern, David J.
year 1988
title Automatic Floorplan Design Using PIAF
source August, 1988. 36 p. : ill. tables
summary This paper presents PIAF (a Package for Intelligent and Algorithmic Floorplanning), developed at Sydney University Electrical Engineering (SUEE) for use in custom integrated circuit design. Floorplanning plays a crucial role in the design of custom integrated circuits. When design is approached in a top-down fashion, the function to be implemented on silicon is first decomposed in a conceptual phase into a Functional Block Diagram (FBD). This FBD has a 'blocks and buses' structure where blocks represent sub- functions and buses represent the interconnections that carry data and other information between blocks. The decomposition of the function into sub-functions is hierarchical and aims at reducing the complexity of the design problem. When the FBD is known, the floorplanning process may be performed. When this task is performed manually, the designer searches for a relative placement of the blocks and for an area and shape for each block to minimize the overall chip layout area while at the same time meeting design constraints such as design tool limitations, interconnection characteristics and technological design rules. PIAF is a knowledge-based system (KBS) that has been developed at SUEE during the last four years. It relies on a strategy that partitions the floorplanning task in a way that allows efficient use of heuristics and specialized design knowledge in the generation and pruning of the solution space. This paper presents the operation of PIAF and discusses several implementation issues including; KBS structure, knowledge representation, knowledge acquisition, current context memory design, design quality factors and explanation facility. This paper uses a running example to present the operation of each PIAF's KBS-based solving phases
keywords knowledge, representation, knowledge acquisition, electrical engineering, design, integrated circuits, knowledge base, systems, layout, synthesis
series CADline
references Content-type: text/plain
last changed 2003/06/02 08:24
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